1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to a combination FINFET and planar FET semiconductor device and various methods of making such a device.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If a voltage that is less than the threshold voltage of the device is applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when a voltage that is equal to or greater than the threshold voltage of the device is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region. The above description is applicable for both the N-type FET as well as the P-type FET, except that the polarity of voltage in operation and the doping type of the source, the channel and the drain regions are correspondingly reversed. In so-called CMOS (Complementary Metal Oxide Semiconductor) technology, both N-type and P-type MOSFETs (which are referred to as being “complementary” to each other) are used in integrated circuit products. CMOS technology is the dominant technology as it relates to the manufacture of almost all current-day large scale logic and memory circuits.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the channel from being adversely affected by the electrical potential of the drain, which is commonly referred to as a “punch-through” of the electrical potential from the drain to the source and leads to larger leakage currents. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, which has a planar structure, there are so-called three-dimensional (3D) devices, such as an illustrative FinFET device, which is a three-dimensional structure. More specifically, in a FinFET, a generally vertically positioned, fin-shaped active area is formed and a gate electrode encloses both of the sides and the upper surface of the fin-shaped active area to form a “tri-gate” structure so as to use a channel having a 3D “fin” structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the depletion width in the “fin” channel (as a result of the better electrostatic characteristics of the tri-gate or dual-gate structure around the fin channel) and thereby reduce so-called short channel effects. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects.
In one embodiment, FinFET devices have been formed on so-called silicon-on-insulator (SOI) substrates. An SOI substrate includes a bulk silicon layer, an active layer and a buried insulation layer made of silicon dioxide (a so-called “BOX” layer) positioned between the bulk silicon layer and the active layer. Semiconductor devices are formed in and above the active layer of an SOI substrate. The fins are formed in the active layer and the buried insulation layer provides good isolation between adjacent fins. The processes used to form FinFET devices on SOI substrates have relatively good compatibility with various processes that are performed when forming planar transistor devices in CMOS applications. For example, in both applications, the gate stack and the gate insulation layer can be made of the same materials (as in planar CMOS on SOI), e.g., poly-SiON or high-k/metal-gate (HKMG), and both applications may involve performing various epitaxial silicon growth processes (e.g., SiGe for PMOS and raised SD for NMOS) as well as the formation of epi-silicon material on the fins so as to define the source/drain regions from the FinFET devices that provide good resistance and desirable stress characteristics. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins, i.e., the substantially vertically oriented sidewalls and the top upper surface of the fin with inversion carriers, contributes to current conduction. In a FinFET device, the “channel-width” is approximately two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly stronger drive current than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar transistor MOSFETs due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar MOSFET, especially in the 20 nm CMOS technology node and beyond.
Recently, device manufacturers have become more interested in forming FinFET devices on bulk silicon substrates in an effort to reduce costs and to make the FinFET formation processes more compatible with planar CMOS process operations. However, use of a bulk substrate typically requires the formation of shallow trench isolation (STI) regions in the substrate to electrically isolate the devices. The fins of a FinFET device only need to have a relatively shallow or small fin height, e.g., about 20-40 nm. In contrast, the STI regions that are formed to electrically isolate adjacent FinFET devices are typically required to be much deeper (or taller), e.g., about 100-300 nm, than the height of the fins. Typically, a plurality of trenches are formed in the substrate to define the areas where STI regions will be formed and to define the initial structure of the fins, and these trenches are typically formed in the substrate during the same process operation for processing simplicity. The trenches are desirably designed with the same pitch (for better resolution during lithography) and they are formed to the same depth and width (for processing simplicity), wherein the depth of the trenches is sufficient for the needed fin height and deep enough to allow formation of an effective STI region. After the trenches are formed, a layer of insulating material, such as silicon dioxide, is formed so as to overfill the trenches. A chemical mechanical polishing (CMP) process is then performed to planarize the upper surface of the insulating material with the top of the fins (or the top of a patterned hard mask). Thereafter, an etch-back process is performed to recess the layer of insulating material between the fins and thereby expose the upper portions of the fins, which corresponds to the final fin height of the fins.
However, as the dimensions of the fins and the fin-pitch on FinFET devices has decreased, problems arose with manufacturing the isolation structures and fins formed at the same process step with the same pitch and same trench depth. One possible solution that was attempted to address this problem was to form the very small fins in regions that were separated by relatively larger isolation regions. However, this approach was difficult to implement in production due to the formation of “fatter” fins, or fins having an abnormal profile, immediately adjacent to the larger isolation region than those fins not immediately adjacent to the larger isolation region. The formation of such “fatter” or abnormal fins was due, at least in part, to the non-uniform spacing between various structures on the substrate. The formation of such “fatter” or abnormal fins (sometimes referred to as the “first fin” effect) resulted in large variations in the threshold voltage of FinFET devices, a characteristic which is highly undesirable in conventional FinFET technology. Other problems include high defect density (broken fins), difficult gap-fill (small pitch and high aspect ratio) and variations in fin profile, etc. One manufacturing technique that is employed in manufacturing FinFET devices so as to eliminate the “first fin” effect is to initially form a so-called “sea-of-fins” (with equal fin width and spacing or fin pitch everywhere) across the substrate, and thereafter performing an extra masking and etching step to remove some of the fins where larger isolation structures will be formed. Using this “sea-of-fins” type manufacturing approach, better accuracy and uniformity may be achieved in forming the fins to very small dimensions due to the more uniform environment in which the lithography and etching processes that form the trenches that define the fins is performed. As mentioned, after the “sea-of-fins” has been formed, an extra mask layer was formed and an extra etching process was performed to remove some of the fins to create room for or define the spaces where isolation regions will ultimately be formed, which increases the cost and processing complexity of such an approach.
The formation of planar transistor devices in CMOS technology has also evolved and continues to evolve to produce devices with improved operational characteristics. One relatively recent advance involves the use of low channel doping (i.e., super-steep channel doping profiles) for deeply depleted channel regions during device operation, where there are multiple epi layers (i.e., Boron-doped-Silicon (Si:B), Carbon-doped Silicon (Si:C) and non-doped Silicon) formed above N/P wells. In such a device, the suppression of boron (B). phosphorous (P) and arsenic (As) diffusion is mainly due to the presence of the carbon-doped silicon layer (Si:C) layer. Alternatively, instead of using epitaxial growth processes, the B-doped and C-doped silicon layers can be formed by implanting boron and carbon into the silicon substrate. The low doping of the channel region may suppress or reduce the so-called “short-channel effect” typically found on traditional planar transistor devices manufactured on bulk silicon, reduce variations in the threshold voltages of such devices (due to less random dopant fluctuations), reduce source/drain leakage currents (by punch-through suppression by those doped layers below the channel) and lower junction capacitances. Therefore, MOSFET devices formed on a bulk substrate with a low doped channel can enjoy the advantages of devices with fully depleted channel regions during operations as if they are fabricated on an SOI substrate.
It is generally known that fully depleted devices with a substantially un-doped or low-doped channel region are effective in reducing threshold voltage variability due to the elimination of random dopant fluctuations in such devices, and that such devices exhibit improved device performance with relatively low dynamic power requirements, low leakage currents and relatively high transistor density. The fully depleted devices can take the form of planar transistor devices with ultra-thin bodies formed on SOI substrates or three-dimensional devices, such as FINFET devices. However, the planar devices consume a substantial amount of plot space (or foot-print) in the channel width direction and, with respect to FINFET technology, there are significant challenges in forming deep fin/isolation trenches and filling such trenches without creating undesirable voids.
The present disclosure is directed to a combination FINFET and planar FET semiconductor device and various methods of making such a device that may solve or reduce one or more of the problems identified above.